The ever-increasing demand for large-size color television receivers has led to the development of large-sized direct viewing CRT-type color television receivers larger than 30". However, because CRTs that are larger than 30" increase in weight drastically, the 30" type CRT is considered to be the largest size available for practical use.
On the other hand, because the projection type color television receivers project a picture from projection tubes (CRT) through a lens system for magnification, they can be designed relatively compact in size and relatively light in weight. The projection type television receivers have therefore become the mainstream in color television receivers that exceed 40".
The projection type color television receiver has monochrome projection picture tubes of R (red), G (green) and B (blue). The video signals in R (red), G (green) and B (blue) are supplied to respective projection tubes which are linearly aligned. R, G and B images on respective projection tubes are magnified, projected and imaged on a screen through an optical system comprising lenses, reflectors, etc. However, some color deviations are induced in the projected image on the screen due to the different angles of incidence of beams emitted from respective projection tubes onto the screen, an alignment deviation of the three monochrome projection tubes, unmatching of orbits of the electron beams due to the earth magnetism, etc. To overcome the improper convergence, a convergence correction apparatus is provided to focus R, G and B image electron beams on the screen. The convergence correction apparatus corrects the deviation angles of the electron beams by applying the correction field through the convergence correction coil provided to the projection tube of each axis.
FIG. 8 is an explanatory diagram showing one example of such conventional projection type television receiver, while FIG. 9 is an explanatory diagram showing the arrangement of R, G and B projection tubes in such conventional projection type television receiver.
In FIG. 8 a screen 2 is provided on the upper front side in a cabinet 1. A chassis (not shown) is installed on the floor of the cabinet 1, and an image receiving circuit (not shown), etc. is mounted on the chassis. Supporting members (not shown) are mounted within the cabinet 1, so as that the R, G and B projection tubes 3R, 3G and 3B are supported on these supporting members when installed in the cabinet 1. R, G and B image electron beams are emitted from the R, G and B projection tubes 3R, 3G and 3B in response to the image signals provided from the image receiving circuit. The image electron beams emitted from the projection tubes 3R, 3G and 3B are reflected by a reflection mirror 4 mounted on the front surface of the cabinet 1 and a reflection mirror 5 mounted on the rear surface through projection lens 6R, 6G and 6B, respectively, before being projected on the screen 2.
FIG. 9 shows the orientations of the projection tubes 3R, 3G and 3B viewed from the top of the cabinet 1. The R, G and B projection tubes 3R, 3G and 3B are aligned in a horizontal line parallel to the screen 2, as shown in FIG. 9. Further, the projection tubes 3R, 3G and 3B are so arranged that their optical axes join to each other in consideration of the structure of the optical system. The R, G and B image electron beams from the projection tubes 3R, 3G and 3B are emitted through respective projection lenses 6R, 6G and 6B to form images on the screen 2. A magnified color image is thus displayed on the screen.
A display unit employing a digital convergence apparatus is higher in cost than analog type convergence apparatus. It is easy to correct and has higher correction accuracy. Also, use of the digital convergence apparatus is increasing in these years. FIG. 10 is a block diagram showing a color television receiver with such a conventional digital convergence apparatus. In FIG. 10, only the R image section is shown. Other G and B image sections have a similar structure to the R image section.
The apparatus as shown in FIG. 10 forms an image of a convergence correction pattern on a screen, corrects the color deviation of each part shown on the screen by correcting the convergence, stores the correction data of each part for one field in a memory, generates a correction signal from the correction data read out in synchronization with the scanning of the screen and provides the correction signal as the correction current to the convergence correction coil.
A grid pattern, generally called as a crosshatch pattern, is often used for the correction of convergence. In a manufacturing process, an operator carries out convergence correction by manipulating an adjusting tool while observing the convergence correction grid pattern on the screen. Normally, all intersecting points of the vertical and horizontal lines of the convergence correction pattern define the correction executing points where the convergence corrections can be made. The operator selects any one or plural correction executing points and then carries out the correction so as to reduce the color deviation at the correction executing points using the adjusting tool.
FIGS. 11(a) through 11(c) are explanatory diagrams showing the crosshatch patterns displayed on the screen by the R, G and B projection tubes before the convergence correction is performed. FIGS. 11(a) through 11(c) show patterns displayed on the screen by the projection tubes 3R, 3G and 3B of respective axes. Such distortions of the crosshatch patterns are induced due to the optical system characteristic attributable mainly to the lenses, as shown in FIGS. 11(a) through 11(c). Thus, correction currents consistent with the distortions are supplied to convergence correction coils to reduce the color deviations.
In FIG. 10, the high frequency television signal (RF signal) induced on an antenna 11 is received by a tuner 12, which selects a prescribed channel under the control of a channel selector 13. The tuner 12 converts the RF signal into the intermediate frequency signal (IF signal), and then supplies the IF signal to a detector/amplifier unit 14. After detected and amplified by the detector/amplifier unit 14, the IF signal is provided to a signal processor IC 15.
The signal processor IC 15 converts the input baseband video signals into R, G and B signals by executing a video signal processing, a chromatic processing and a synchronizing deflection processing to the baseband video signal. The R signal is supplied to a projection tube driver 16. The signal processor IC 15 gives the horizontal pulse H separated from video signals to a horizontal driver 17 and a high voltage driver 18, and gives the vertical pulse V to a vertical output unit 19.
A deflection driver 20 is comprised of the horizontal driver 17, a horizontal output unit 21, a horizontal output transformer 22 and the vertical output unit 19. The horizontal driver 17 gives the horizontal driving pulse of the horizontal period to the horizontal output unit 21, which generates the sawtooth wave current of the horizontal period and gives it to a horizontal deflection coil 23. This sawtooth wave current is also provided to an intermediate voltage and a low voltage power units (not shown) via the horizontal output transformer 22. Further, the horizontal driving pulse HD of the horizontal period is also provided to a convergence corrector 25 from the horizontal output transformer 22. On the other hand, the vertical output unit 19 generates the sawtooth wave current of the vertical period from the vertical pulses and provides the current to a vertical deflection coil 24. The vertical output unit 19 also generates the vertical driving pulse VD of the vertical period and provides the pulse VD to the convergence corrector 25.
The convergence corrector 25 is equipped with a memory having the capacity of one field, in which convergence correction data for generating the convergence correction currents are stored. The convergence corrector 25, when provided with the horizontal and vertical driving pulses HD and VD, reads data out of the memory in synchronization with the scanning of the screen and generates the correction current based on the read data. This correction current is provided to a convergence correction coil 32 via a driving amplifier 31 to correct the distortion on the screen. Further, two convergence correction coils for the horizontal deflection and the vertical deflection are provided for each of the three of the R, G and B sections, a driving amplifier 31 being provided for each of the convergence correction coils. Accordingly, total six driving amplifiers are provided.
The projection tube driver 16 drives a projection tube 29 according to the R-signal. The horizontal and vertical deflections of the projection tube 29 are controlled by the horizontal and vertical deflection coils 23 and 24 and the convergence correction coil 32. Thus an image associated with the R-signal is emitted from the projection tube 29. The high voltage bias for the projection tube 29 is generated by a high voltage generator 28, which is comprised of the high voltage driver 18, a high voltage output unit 26 and a flyback transformer 27. The high voltage driver 18 provides the pulse with the horizontal period to the high voltage output unit 26, which provides the current with the horizontal period to the flyback transformer 27 to generate the high voltage bias output from the flyback transformer 27 during the horizontal retrace line period. This high voltage bias output is provided to an anode 30 of the projection tube 29.
The high voltage bias output from the high voltage generator 28 is detected by a resistance type voltage divider composing of resistors R1 and R2. The voltage on the connecting point of the resistors R1 and R2 is input to a comparator 35, where a high voltage fluctuation component is detected by comparing the input voltage with the reference voltage. The high voltage fluctuation component is supplied to a high voltage controller 33. The high voltage controller 33 comprises a control transistor and a saturable reactor (not shown). It operates to make the high voltage fluctuating component zero by controlling the primary winding voltage of the flyback component. A high voltage stabilizer 34 is composed by the divider including the resistors R1 and R2, the comparator 35 and the high voltage controller 33.
FIG. 12 is a block diagram showing the definite construction of the convergence corrector 25 shown in FIG. 10.
Correction data of the correction executing points on the crosshatch pattern are obtained and stored in a data storage 41 in the manufacturing process of the projection type projector, etc. before shipping. When the power source of the projection type projector, etc. are turned on, a control microcomputer 42 controls a data transfer controller 43 to transfer the correction data of the correction executing points stored in the data storage 41 to a field memory 44. A selector 45 is controlled by the data transfer controller 43 to select either one of the write address from the data transfer controller 43 or the read address from a read address generator 46, and to provide the selected address to the field memory 44. In transferring the data, the write address from the data transfer controller 43 is selected by the selector 45.
When the transferring of the correction data to the field memory 44 is completed, the data transfer controller 43 provides the read address from the read address generator 46 to the field memory 44 by controlling the selector 45. The read address generator 46, to which the horizontal and vertical synchronizing signals are input, match the correction data which is output from the field memory 44 to a position on a screen by generating the read address in synchronization with the horizontal and vertical scannings. The correction data are provided to an adder 47 when output, in order, from the field memory 44.
Although deviations of static convergence induced due to the assembling tolerance of an electron gun, etc. can be corrected using the correction data, the deviation of the static convergence may be induced due to the earth magnetism due to the installing direction, secular change, etc. Because these factors are often unpredictable during the manufacturing process, the correction data stored in data storage 41 does not account for or correct these deviations. Hence, the convergence deviation may not be certainly corrected using the correction data stored in the data storage 41. So, a static convergence correction data which is adjustable by an operator is added to the correction data to correct this static convergence deviation.
A static convergence correction data output unit 48 maintains static convergence correction data. The static convergence correction data is a data showing the amount of movement in the horizontal and vertical directions and is set for each of R, G and B colors. That is, the static convergence correction data is comprised of 6 kinds of data, each of which is comprised of one word. Therefore, the static convergence correction data output unit 48 is provided with a memory having the capacity to store 6 words for the adjusting colors R, G and B in the horizontal and vertical directions. The static convergence correction data output unit 48 outputs the static convergence correction data to the adder 47 corresponding to the correction data provided from the field memory 44.
Further, as described above, it is possible to modify the static convergence data by an operator. The control microcomputer 42 is capable of modifying the static convergence data by giving data to the static convergence correction data output unit 48 using an entry unit 49 such as a remote controller. The adder 47 outputs the correction data from the field memory 44 to a vertical interpolator 50 with the static convergence correction data added.
The correction executing points properly assigned on scattered locations on a screen to reduce the capacity of the field memory 44 and a correction data between the correction executing points is obtained by the interpolation. That is, the vertical interpolator 50 obtains a correction data between the correction executing points in the vertical direction by interpolating the correction data in the vertical direction. As a result, a correction data corresponding to each scanning line is output from the vertical interpolator 50. A D/A converter 51 converts the correction data from the vertical interpolator 50 into analog signals, and a low-pass filter (hereinafter referred to as LPF) 52 smooths the correction data in the horizontal direction by removing the harmonic component and provides to the convergence correction coil 32.
In the normal video display, a selector 55 provides video signals to a display 57 under the control of the control microcomputer 42, and the convergence correction coil 32 displays an image on the screen (not shown) without the color deviation by deflecting beam current corresponding to the correction voltage. Two kinds of convergence correction coils 32 are respectively provided for the horizontal and vertical directions. The correction signal provided to the horizontal convergence correction coil displaces electron beams to the left at the positive polarity and to the right at the negative polarity. The correction signal provided to the vertical convergence correction coil displaces electron beams in the downward direction at the positive polarity and in the upward direction at the negative polarity.
In the following, the convergence correction will be described in detail.
A pattern generator 56 is provided with the output of the read address generator 46. Using this output, pattern generator 56 generates a pattern signal for displaying a convergence correction pattern such as a crosshatch pattern and outputs it to the selector 55. When an operator manipulates the entry unit 49 to direct the start of the convergence correction, the control microcomputer 42 controls the selector 55 to select the output of the pattern generator 56. Thus, a pattern signal is provided to a display 57 and a convergence correction pattern is displayed on the screen (not shown).
The operator makes the correction to reduce color deviations at the correction executing points by manipulating the entry unit 49 while observing the correction pattern displayed on the screen. The information on this correction is supplied to the field memory 44 and the data storage 41 as the correction data via the control microcomputer 42. The field memory 44 stores the correction data at all the selected correction executing points displayed on the screen and outputs the correction data in synchronization with the screen scanning under the control of the data transfer controller 43. Likewise, the normal video display operation, the correction data read out of the field memory 44 is supplied to the convergence correction coil 32 via the vertical interpolator 50, the D/A converter 51, the LPF 52 and the amplifier 53. Thus, the color deviation at each part of the screen is adjusted.
The operator makes the correction at each correction executing point using the entry unit 49 so that the color deviation is minimized. As a result of the correction, the correction data stored in the field memory 44 and the data storage 41 are updated in order and the adjusted correction data for each correction executing point is stored in the data storage 41. Thus, in the normal video display operation, it becomes possible to display video on the screen at a satisfactory convergence by reading the correction data stored in the data storage 41.
FIG. 13 is a block diagram showing a definite construction of the vertical interpolator 50 shown in FIG. 12. The circuit shown in FIG. 13 is disclosed in the Japanese Patent Application, Tokkai-Sho No. 58-01586.
In the circuit shown in FIG. 13, it is assumed that the correction data at the correction executing points and the difference between the correction data at the correction executing points are stored in the field memory 44. FIG. 14 is an explanatory diagram showing the screen display when a crosshatch pattern from the pattern generator 56 is supplied to the display 57. The intersecting points of the crosshatch pattern are the correction executing points. FIG. 14 indicates that 5 vertical points and 7 horizontal points, a total 35 correction executing points, are assigned. Correction data for 35 correction executing points are stored in the field memory 44.
Now it is assumed that correction data to correct the convergence at the correction executing points are D00 through D60, D01 through D61, . . . D04 through D64 as shown in FIG. 15. The correction data D00 through D60 on the first line (hereinafter referred to as the first adjusting line) of the crosshatch are stored in the corresponding locations in the field memory 44. As to the second line of the crosshatch (hereinafter referred to as the second adjusting line) and subsequent lines, the difference between the correction data of the Lth line of the crosshatch (hereinafter referred to as the Lth adjusting line) and the correction data of the (L-1)th adjusting line is obtained for each line. The obtained differential data is stored in the corresponding location in the field memory 44. For instance, the differential data d02 through d62 between the correction data D02 through D62 of the third adjusting line and the correction data D01 through D61 of the second adjusting line are stored in the field memory 44 as the correction data of the third adjusting line. Thus, the data shown in FIG. 16 are stored in the field memory 44.
With reference to FIG. 13, the read address generator 46 is comprised of a Y address counter 61, an X address counter and a frequency divider 63. The frequency divider 63 starts the 2/n frequency division after being cleared by a vertical sync signal. The first horizontal sync signal is then input after the vertical sync signal is input. That is, the frequency divider 63 counts a horizontal sync signal subsequent to the second horizontal sync signal after the vertical sync signal is input, and carries out the 2/n frequency division by outputting one clock at every n/2 counting, "n" representing the number of scanning lines between the correction executing points in the vertical direction.
The output of the frequency divider 63 is supplied to the Y address counter 61. The Y address counter 61 is cleared by a vertical sync signal. After being cleared, Y address counter 61 counts the output of the frequency divider 63 and outputs the count to the field memory 44 via the selector 45. For instance, if the number of valid scanning lines of a video signal in the frame is 480 lines and 5 adjusting lines are assigned per one frame, "n" is 80 lines in the frame. As data for one field is stored in the field memory 44, data corresponding to the scanning of the screen can be read out when Y address is updated for every n/2 scanning line (40 scanning lines).
The X address counter 62 is cleared by a horizontal sync signal. After being cleared, X address counter 62 counts a clock CLK and outputs the count to the field memory 44 as an X address via the selector 45. The clock CLK represents a clock having pulses of m pieces of the correction executing points in the horizontal direction in one horizontal scanning period (e.g., m=7 in FIG. 14).
The adder 47 adds a static convergence correction data from the static convergence correction data output unit 48 to the data read out of the field memory 44 and outputs the added data to a vertical interpolator 50. The adder 47 adds a static convergence correction data S only when the correction data of the correction executing point of the first adjusting line is read out of the field memory 44.
The vertical interpolator 50 is comprised of a divider 65, an adder 66, a register 67 and a latch 68. The divider 65 divides the output of the adder 47 by 2/n or 1/1, and outputs the result of the division to the adder 66. The divisor n/2 of the divider 65 is consistent with the frequency division ratio of the frequency divider 63. The adder 66 adds the output of the latch 68, which will be described later, to the output of the divider 65 and outputs the result to the register 67. The register 67 is provided with X address; it stores m pieces of data from the adder 66 and outputs them to the latch 68. Further, at the time when the vertical scanning period started, all the data retained in the register 67 represent zero (0). The output of the adder 66 is delayed by one horizontal scanning period through the register 67 and applied to the latch 68. The latch 68 latches the output of the register 67 by the clock CLK and outputs it to the adder 66 and the D/A converter 51.
According to this construction, the count output of the Y address counter 61 indicates zero (0). That is, at the timing at the uppermost part of the frame, the Y address counter 61 outputs Y address 0 for reading the correction data of the first adjusting line of the field memory 44. On the other hand, the X address counter 62 counts m pieces of clock CLK generated in one horizontal scanning period and outputs it as the X address. That is, the correction data D00 of the first correction executing point of the first adjusting line of the field memory 44 is read out by the input of the clock CLK immediately after the horizontal sync signal.
The read correction data D00 is supplied to the divider 65 after being added with a static convergence correction data S in the adder 47. At this time, the divisor of the divider 65 is 1 and the correction data D00+S is supplied to the adder 66 as it is. Further, at this time, the correction data D00+S that is input to the adder 66 is stored in the register 67 to replace the zeros previously stored there. Thereafter, the X address increases as the clock CLK is input, the correction data D10 through D60 of the field memory 44 are read out in order and stored in the register 67 after being added with the static convergence correction data S.
In the next horizontal scanning period, the frequency divider 63 starts the 2/n frequency division of the horizontal sync signal. The output of the Y address counter 61 becomes 1 and the differential data d01 through d61 of the correction executing points of the second adjusting line of the field memory 44 are read out in order every time when the clock CLK is input. The differential data d01 through d61 are supplied to the divider 65 without the static convergence correction data S added. The divisor of the divider 65 at this time is n/2 and the differential data d01 through d61 are multiplied by 2/n and output to the adder 66.
The data stored in the register 67 for the preceding horizontal scanning period is output via the latch 68 in this horizontal scanning period. The adder 66 adds the differential data 2.times.d01/n from the divider 65 to the correction data stored in the register 67 and stores the added result in the register 67. Similarly, the adder 66 adds the differential data (2.times.d11/n) through (2.times.d61/n) to the correction data (D10+S) through (D60+S), respectively, which are stored in the register 67 and stores the added results in the register 67.
In the next horizontal scanning period, the output of the Y address counter 61 is also 1. Accordingly, the differential data d01 through d61 of the second adjusting line, which are stored in the field memory 44, are read out in order every time when the clock CLK is input. The differential data is supplied to the divider 65 via the adder 47 and after being multiplied by 2/n, it is supplied to the adder 66. When the data (2.times.d01/n) is input to the adder 66, the data (D00+S+2.times.d01/n) stored in the register 67 is input to the adder 66 from the latch 68, and the adder 66 adds up both data and supplies the data (D00+S+2.times.2.times.d01/n) to the register 67 for retention. Similarly, the data (D10+S+2.times.2.times.d11/n) through (D60+S+2.times.2.times.d61/n) are stored in the register 67 every time when the clock CLK is input.
Hereinafter, until a data "2" is output from the Y address counter 61 in the similar manner, the data of m (=7) pieces stored in the register 67 become larger by (2.times.d02/n) through (2.times.d62/n), respectively. When address 1 is output by n/2 times from the Y address counter 61, the data (D00+S+d01) through (D60+S+d61), that is, (D01+S) through (D61+S) are stored in the register 67. As a result, the correction data for the correction executing points of the second adjusting line are reproduced.
When the frequency divider 63 counts the n/2 pieces of horizontal sync signals and outputs the pulse to the Y address counter 61, the address of the Y address counter 61 becomes 2. As a result, the differential data d02 through d62 of the third adjusting line of the field memory 44 are read out in order whenever the clock CLK is input. Thereafter, until such a time when the same operation is repeated and the address of the Y address counter 61 becomes 3, data of m=7 pieces stored in the register 67 become larger by (2.times.d02/n) through (2.times.d62/n), respectively. Thus, after the n/2 pieces of clocks CLK, the data (D02+S) through (D62+S) are restored in the register 67.
The data stored in the register 67 are output to the D/A converter 51 via the latch 68 in the next horizontal scanning period. The correction data of the correction executing points of the adjusting lines are interpolated linearly for each scanning line and output from the register 67. Further, an interpolation data of the Y adjusting line from the prescribed correction executing point Dxy is expressed by the following expression (1). EQU Dxy+2.times.dx(y+1).times.Y/n+S (1)
FIG. 17 is a graph showing the interpolation status with the convergence correction signal levels plotted on the vertical axis and the time base on the horizontal axis at the valid number of scanning lines 0 through 240, for each field shown in full scale with one horizontal scanning period as a unit. The white circles in the figure show the correction data of the correction executing points of the vertical one row at the prescribed horizontal location on the screen. For instance, the white circles correspond to correction data such as that of any of D00 through D04. Further, FIG. 17 shows an example where 7 correction executing points are assigned in the vertical direction. As described above, correction data at the correction executing points are interpolated linearly between these white circles for each horizontal scanning so that the correction signal can be output for all horizontal scanning periods.
As described above, on a conventional digital convergence apparatus, a correction signal is obtained for each scanning line and the position of the scanning line is corrected by controlling the deflection of electron beam on the basis of the correction signal. However, there was such a problem that the lateral stripes of the scanning lines become conspicuous as the same correction signal is used in both the odd field and the even field.
FIG. 18 is a diagram for explaining this problem. The square marks in FIG. 18 represent the scanning line positions before the correction in the odd and even fields, while the circles represent the scanning line positions after the correction. FIG. 18 shows the correction of the scanning line positions in the vertical direction in response to the correction signals.
In FIG. 18, it is shown that the scanning lines A1, A2, . . . in the odd field before the correction, were moved in the vertical direction by, for instance, +12, +8, +4, 0, -4, -8 and -12. The "+" sign represents the upward direction, while the "-" sign represents the downward direction. By this correction, the scanning lines A1', A2', . . . in the odd field are displaced to the positions with the circles. On the other hand, the same correction is performed for the scanning lines B1m B2, . . . in the even field. That is, the scanning lines B1, B2, . . . in the even field are moved in the vertical direction by +12, +8, +4, 0, -4, -8 and -12, respectively. As a result, the scanning lines B1', B2'. . . in the even field are displaced to the positions shown by the circles.
However, as a result of this correction, the distances between the scanning lines comprising one frame will become no longer uniform. For instance, the distance between the scanning lines A1' and B1' after the correction is narrow and the distance between the scanning lines B1' and A2' after the correction is wide as shown in FIG. 18. That is, as an interlaced scanning was carried out, the density of the scanning lines in a frame is made rough and fine as a result of the same correction in the odd and even fields and the lateral stripes of the scanning lines become conspicuous, thus deteriorating the quality of picture. In particular, on projection type television receivers with a large screen, there was a problem that the quality of picture deteriorates remarkably.
On a conventional digital convergence apparatus as described above, there was such a problem that the density of the scanning lines lacks uniformity as a result of using the same correction data in the odd and even fields, making the lateral stripes conspicuous, and thus the quality of picture is deteriorated.